1) Field of the Invention
This invention relates to an electrically programmable read only memory (EPROM) device and a method of making this device which has high efficiency of electron injection to the floating gate.
2) Description of the Prior Art
The channel hot electron (CHE) injection transistor with step split was described and claimed in Seiki Ogura U.S. Pat. No. 5,780.341. The effective horizontal channel length under the floating gate of that US Patent was designed to be very short.
M. Kamiya et al xe2x80x9cEEPROM Cell With High gate injection Efficiencyxe2x80x9d published in IEDM, 1982, page 741 describes conventional split gate source-side injection transistor.
Y. Yamauchi, xe2x80x9cA 5V-Only Virtual Ground Flash Cell with An Auxiliary Gate for High Density and High Speed Applicationxe2x80x9d, published in IEDM 1991, page 11.7.1 describes a Flash EEPROM device and method for making the device. The memory device seems similar to the present invention, but is structurally different and the method for fabricating is much different. Further, the device cannot give the efficiency of electron injection from channel to floating gate that is possible in the present invention.
The short channel step device of the Ogura U.S. Pat. No. 5,780,341 has given a few orders of injection efficiency improvement over conventional source side injection devices. However, it has also been found that this short channel split gate device has very high injection efficiency, at low voltages, even without the step. The planar short channel split gate device of the present invention has been found to have an injection efficiency of one order less than that for a step device, at similar low voltages and currents. The reduced process complexity for the planar short channel device is advantageous where injection can be slightly slower than, but still operate at low voltages similar to the step device. Simulation analysis reveals that the programming mechanism for the short channel split gate device is very different from the conventional split gate source-side injection transistor described by M. Kamiya et al cited above, even though the structures may resemble each other as seen in the Yamauchi cited above.
For a split gate device in which the distance between word gate to n-region (effective FG horizontal channel) is less than about 100 nm (preferably less than about 50 nm), and defined by a controllable double side wall technique, high injection efficiency can be obtained by photon scattering without undesirable channel electron-electron scattering effects. The injection mechanism of this transistor is characterized by:
(i) the effective FG horizontal channel is almost completely depleted by a drain voltage of 3.2V the oxide barrier height is 3.2 eV, therefor, the drain voltage of about 3.2V is required to create high energy electrons cross the oxide barrier for substrate bias of 0 volts, and
(ii) Electron injection begins when the floating gate potential is almost the same as the 3.2V minimum drain voltage.
The device structure obtained by this double side wall technique of this invention resembles the side wall floating gate split device of Yamauchi cited above. Both have horizontally planar channels. However, the device operation for this short channel device of the invention is completely different from the conventional split gate source side injection transistor. Until now, the distance between the word gate edge and the N junction edge has been larger than 0.15 microns, even for the split-side wall gate transistor as shown by Yamauchi cited above. As a result, it has been necessary to raise the voltage of the side wall floating gate to pass the drain voltage through. For example, in order to create 3.2V near the oxide gap under the floating gate, (close to the oxide barrier height for injection), the floating gate voltage must be at least 3.2V+VT (1 .3V)=4.5V. When the length of the overlapped N region is close to that of the channel length, and the coupling ratio from drain to floating gate is about 0.5, the drain voltage has to be 7V with word gate voltage of 2V, in order to obtain the 4.5V floating gate voltage required for reasonable programming speed.
On the other hand, the channel of the new device of the invention is very short, less than about 100 nm (and preferably less than about 50 nm), and the N drain is very close to the word gate edge. In this structure, at a drain voltage of 3.2V and floating gate of 3.2V, the enhanced channel becomes almost completely depleted, achieving good programming conditions without the higher floating gate voltage requirement. Coupling ratios are actually improved by the smaller channel length. Assuming a coupling ratio of 0.5 for consistency, a drain voltage of 4.4V is required to achieve floating gate voltage of 3.2V. Further improvement of the coupling ratio can obtain good programming conditions even for a low drain voltage of 4V. Thus, this new double side wall short channel device of the present invention reduces the drain voltage requirement for source side injection operation from 7V to 4V. This reduced high voltage requirement will ease charge pump design, and improve scalability.
Unlike the conventional split gate transistor in which polysilicon width is optically defined to be about 30% of the minimum ground rule, definition of the floating gate dimensions for the new device of the invention is defined by the side wall spacer technique. The side wall spacer technique used by the method of the invention is very controllable to within a few percent (+/xe2x88x925%).
By utilizing the side wall technique twice in the method of the invention, a very short enhancement mode channel of less than about 100 nm (preferably less than about 50 nm), and an N/N+ region which is a few times larger, can be precisely formed.
(i) A precisely controllable, very short enhanced mode channel (less than about 50 nm) with profile about 5E17cm2, is almost completely depleted when 3V is applied to the drain and the floating gate voltage is also around 3V.
(ii) Since the N/N+ region under the floating gate is few times larger (between about 150 to 300 nm), capacitive coupling only needs to raise the floating gate potential to be close to 3V, with the drain voltage of 4V, which can be easily achieved. By comparison Source Side Injection device requires at least 7V.
(iii) Since 3.2V is applied over this less than about 100 nm channel, a very high electric field of about 5E5V/cm is created and electrons that are released from the word gate edge achieve high energy and inject into the floating gate (barrier height=about 3.1 eV).
(iv) Thus this less than about 100 nm short channel utilizing the double side wall technique provides high electron injection efficiency at low gate and drain voltages of about 3V, reducing the high voltage requirement by almost half compared to the Source Side injection transistor.
The method of fabricating an electrically programmable split gate memory device which has efficiency of electron injection from the channel to floating gate is accomplished with reduced process complexity and consistently reproducible results. The method provides a substrate having a source region with an adjacent channel and a control gate over said channel. A drain region is formed having a floating gate beside said control gate, separated by a oxide layer from said control gate, said floating gate is located over said drain region. The horizontal distance between the vertical edge of said control gate to the closest edge of said drain is less than about 100 nm (preferably less than about 50 nm). The horizontal distance is reproducible between +/xe2x88x925% because of the use of the side wall spacer technique.
A second method of fabricating an electrically programmable split gate memory device which has efficiency of electron injection from the channel to a floating gate includes the following steps. A substrate is provided having a source region with an adjacent channel and a control gate over said channel. A first floating gate oxide layer is formed over the sidewall of the control gate. A silicon nitride sidewall spacer layer is formed over the first floating gate oxide layer on the sidewall of the control gate. The silicon nitride spacer layer is used as a mask to form an N region within said substrate in the area whereat a floating gate is to be formed. The silicon nitride spacer layer is removed. A second floating gate oxide layer is formed over the substrate. The formation of an N+ drain region within said N region is completed by using the control gate as the mask. The floating gate is formed at the side of the control gate and over said first and second floating gate oxide layers on the side wall of the control gate and the substrate.